1. Technical Field
Embodiments of the present disclosure generally relate to semiconductor integrated circuits and, more particularly, to semiconductor devices and electronic systems including the same.
2. Related Art
Synchronous memory devices operating in synchronization with clock signals have been revealed to improve the operation speed of semiconductor memory devices. Single data rate (SDR) synchronous memory devices among the synchronous memory devices receive or output a single data per a single data pin for one cycle time of the clock signal in synchronization with every rising edge of the clock signal. However, high performance memory devices operating at a higher speed than the SDR synchronous memory devices have been demanded to meet the requirements of high performance electronic systems. Accordingly, double data rate (DDR) synchronous memory devices have been proposed recently.
The DDR synchronous memory devices may receive or output the data twice during a single cycle time of the clock signal. That is, the DDR synchronous memory devices may receive or output the data in synchronization with every rising edge and every falling edge of the clock signal. Thus, the DDR synchronous memory devices may operate at a speed which is twice more than that of the SDR synchronous memory devices even without the increase of the frequency of the clock signal.
Additionally, the semiconductor memory devices may be designed and fabricated to include a test mode function for evaluating the operation thereof. That is, the semiconductor memory devices may be evaluated in a test mode and the test results may be monitored whether the semiconductor memory devices normally operate or not.
The evaluation of the semiconductor memory devices may be performed using a test apparatus. If the semiconductor memory devices operating at a high speed are tested with a low frequency test apparatus, a test time may unnecessarily increase.